Circumferential and lateral web registration control system

ABSTRACT

A control system for controlling registration in a multi-color web-fed printing press system senses register marks which are printed on the web. Any circumferential registration error which is detected by sensors that sense the register marks is translated into a count in a circumferential counter which is coupled to a circumferential motor control circuit. The circumferential motor control circuit drives a stepping motor which in turn drives appropriate gearing to correct for the circumferential misregistration of the web as directed by the count in the circumferential counter. The apparent lateral registration error is then measured in a similar manner and is stored as a count in a lateral counter which corrects for lateral misregistration through a stepping motor and appropriate gearing. The error previously determined in the circumferential register is employed to correct the apparent error in the lateral register so that it represents the true lateral registration error instead of the apparent lateral registration error.

United States Patent 51 3,701,464

Gram 1 Oct. 31, 1972 [54] CIRCUMFERENTIAL AND LATERAL WEB REGISTRATIONvCONTROL Primary Examiner--Robert E. Pulfrey SYSTEM AssistantExaminer-Eugene H. Eickholt [72] Inventor: James N. Crum, Stonington,Conn. Attorney-Yawn and Taro! [7 3] Assignee: Harris-IntertypeCorporation, ABSTRACT clevelandohlo A control system for controllingregistration in a 22 i d; O t, 15,1970 multi-color web-fed printingpress system senses register marks which are printed on the web. Anycir- [211 App]. No.: 81,041

cumferential registration error which is detected by sensors that sensethe register marks is translated into [52] US. Cl. ..226/3, 101/181,101/248 a count in a circumferential counter which is coupled 22 226/31to a circumferential motor control circuit. The cir- 51 16:. Cl ..B4lf5/16, B65h 23/02 cumferenfial motor cqmrol circuit drives Stepping [58]Field of Search ....101/181, 248; 226/16, 30, 31, motor whlch mm nveappropriate gearing to cor- 226/2 3 rect for the circumferentialmisregistratlon of the web as directed by the count in thecircumferential [56] References Cited counter. The apparent lateralregistration error is then measured in a similar manner and is stored asa count UNITED STATES PATENTS in a lateral counter which corrects forlateral misregistration through a stepping motor and appropriate3,570,735 3/1971 KUI'Z ..226/3 g g The error previously determined i thei 2,802,666 8/1957 Crosfield ..226/l6 cumferemial register is employedto correct the 3,594,552 7/197 Aiiamwn 101/181 X parent error in thelateral register so that it represents 3,552,308 1/ 1971 f "101,248 Xthe true lateral registration error instead of the ap- 3,264,983 8/ 1966Lewis et al 101/248 X parent lateral registration 6mm 3,084,621 4/1963Guastavino ..101/248 X 1 2,583,580 l/ 1952 Ludwig ..226/31 17 Claims, 8Drawing Figures CG/WAOL SYSTE/M P'A'TENTED our 3 1 I972 SHEET 1 OF 5/A/VEA/7'0/? JAMES M CPU/14 mmm m mm m% W WW U mm, mm

ATTOP/VE Y6 3.701.464 sum 3 OF 5 FIG.3 4

AME/ u? I @4458 4 CPU/14 v ATTORNEYS PATENTED out 3 1 m2 a mm El i fillll Q A av M iw m u L 5 A 5 U 0 E F V G E r. C .C L N v N N m 0 M 5% L w3 m W mm Wmm fim T W W m w a Z CIRCUMFEREN'IIAL AND LATERAL WEBREGISTRATION CONTROL SYSTEM In a rotary web-fed printing press, theprinting cylinder is adjustable circumferentially to adjust the positionof the image longitudinally of the web and axially to adjust the imagelaterally of the web. During printing in a multi-unit press, it isessential that the various colors printed onto a web by the units of thepress be in proper registration both in a longitudinal direction and ina lateral direction if satisfactory color printing is to be achieved.Various systems have been devised for sensing longitudinal(circumferential) and lateral registration errors in a multi-colorprinting press to determinethe circumferential and the lateraladjustments which must be made.

When the lateral and the circumferential registration errors aredetermined, the true circumferential or the true lateral error may notbe correctly measured whenever there is an error in the other direction.The present invention provides a control system for a multicolor web-fedprinting press in which the measured apparent error in one of theregistrations due to an error in the other is corrected.

It is an object of the present invention to provide a web registrationcontrol system in which a first registration error of a web which isassociated with a first coordinate direction is determined and combinedwith a second registration error of the web which is associated with asecond coordinate direction in order to obtain an accurate registrationindication.

It is also an object of the present invention to provide a multi-colorweb-fed digitally controlled registration system in which a firstregistration error which is associated with a first coordinate directionis determined by scanning register marks on a moving web and this erroris digitally stored in a first counter and a second registration errorwhich is associated with a second coordinate direction is measured byscanning second register marks and this error is digitally stored in asecond counter with the count in the second counter being corrected by afactor corresponding to the count in the first counter in order toobtain a more accurate registration indication.

It is a further object of the present invention to provide a webregistration control system in which the control mechanism forcircumferential registration is controlled by pulsing a first counterwhich contains a circumferential count representing the circumferentialregistration error in which the pulses to the first counter are alsoapplied to a second counter to establish a correction in the secondcounter which is used to indicate lateral registration error forapparent error in the lateral representation introduced by thecircumferential misregistration.

It is an additional object of the present invention to provide amulti-color web registration control system in which a single sensor isutilized to sense circumferential and lateral registration marks and agating and control circuit is employed to grate both circumferential andlateral registration error information to a circumferential and to alateral storage means, respectively.

By way of illustration, a specific embodiment of the present inventionis disclosed in the following specification and the accompanyingdrawings in which:

FIG. 1 is a diagrammatic view which shows a web passing through amulti-color web-fed printing system which has individual lateral andcircumferential correction means for each color printing press of thesystem;

FIG. 1a is an enlarged portion of the web of FIG. 1 which shows theregister marks which are employed for registration compensation;

FIG. 2 is a diagram showing the relative position of a reference and acontrol register mark when the diagram of FIG. 2a applies;

FIG. 2a is a diagram showing wave forms for a leading circumferentialregistration error;

FIG. 3 is a diagram showing the relative position of a reference and acontrol register mark when the .diagram of FIG. 3a applies;

FIG. 3a is a diagram showing wave forms for a lagging circumferentialregistration error; and

FIGS. 4a and 4b are block diagrams of a portion of the control system.

A perfecting multi-color web-fed printing press is showndiagrammatically in FIG. 1 in which lithographic perfecting press units12, 14, 16 and 18 are employed to successively print different colors onthe web 10 which moves through the printing press in the directionindicated by the arrow 20. The press units each comprise upper and lowerprinting units designated by A and B appended to the reference characterfor the press unit and each printing unit has a plate cylinder 21 and ablanket cylinder 22 which prints onto the web. The conventionaldampeners and inkers are not shown.

A perfecting multi-color web-fed printing press is showndiagrammatically in FIG. 1. The press includes a plurality oflithographic perfecting press units 12, l4, l6 and 18 which printdifferent colors onto a web 10 as the web moves through the press in thedirection indicated by the arrow 20. The press units each comprise upperand lower printing units designated by the reference character for thepress unit with the letters A and B appended thereto for the upper andlower units, respectively. Each printing unit has a plate cylinder 21and a blanket cylinder 22. The conventional dampeners and inkers havenot been illustrated in the drawings.

As is well known to those skilled in the art, it is necessary for theimages printed by the units which print on one side of the web to be inaccurate registration with each other. Also, it is often desirable tohave the images printed on the opposite sides of the web registered witheach other so that the images will appear in the proper location whenthe web is cut and folded. conventionally, to adjust the registration ofimages, each printing unit of the press is provided with some type ofmechanism for advancing or retarding the an gular phase of the printingcylinders relative to the web (circumferential registration) and amechanism for shifting the cylinders axially (lateral registration).

In the practice of the present invention, register marks are printed byeach of the printing units for use in detemiining the accuracy ofregistration of the images and making the adjustments necessary tomaintain registration. The register marks printed by the units includecircumferential and lateral registermarks and for all the units, exceptunit 18A, the circumferential marks are designated by the referencecharacter 24a and the lateral registration marks are designated by thereference character 24b. The register marks printed by the upper unit18A are used as reference registration marks and have been designated bythe reference character 28a for the circumferential register mark and28b for the lateral registration mark. The registration marks of thedifferent units are printed along a line which extends transversely ofthe web and the marks printed by each unit are sensed by a correspondingphotoelectric sensor. The sensors for the upper units are designated bythe reference characters 36a, 36b, 36c, 36d, while those for the lowerprinting units have not been shown. It will be understood, however, thatthey are located on the underside of the web and that they operate in amanner similar to the sensors shown for controlling the registration ofthe lower printing units.

As the register marks printed by the printing units pass beneath thecorresponding photoelectric sensor, electric pulse signals are generatedand applied to a control system 40. The pulse signals are generated bythe register mark when it passes the photoelectric sensor and changesthe amount of reflected light received by the sensor from a light source25. The control system 40 determines whether or not the reference marksprinted by the printing unit 18A pass the sensor 36a ahead, behind or atthe same time that the registration marks printed by the other printingunits pass the corresponding sensor for those units. If a register markfrom one of the other units leads or lags the reference mark from theprinting unit 18A, a registration error exists and the control circuitry40 determines the magnitude and direction of the registration error aswell as whether the error is circumferential, lateral, or both.

Following the determination of the magnitude and direction of thecircumferential and lateral registration errors by the control system40, circumferential and lateral control signals are provided to correctthe error in registration. Each printing unit has motor control circuits33 and 35 which control stepping motors 37 and 39, respectively. Thestepping motors 37 are circumferential correction stepping motors whilethe stepping motors 39 are lateral misregistration correction steppingmotors. The stepping motors 37 and 39 for each unit respectively drivegearing systems 41 and 43 for correcting for circumferential and lateralmisregistration, respectively. The gearing systems 41 and 43 are showndiagrammatically in FIG. 1 and a detailed description of these gearingsystems will not be undertaken since they are well known to thoseskilled in the art. vMoreover, only the stepping motors and gearing forthe upper printing unit have been schematically shown but it is to beunderstood that the lower units have corresponding motors and gearingunits.

The manner in which the circumferential and lateral registration errorsis measured is described below with reference to FIGS. 2, 2a, 3 and 3a.FIGS. 2 and 2a illustrate the technique by which the circumferential andthe lateral registration error for a printing unit is determined whenthe circumferential register mark 24a of printing unit 12A leads thecircumferential reference register mark 28a and the lateral registermark 24b of the unit 12A lags the lateral reference register mark 28b.The pulse wave forms of FIG. 2a correspond to the positions of thereference and unit register marks of FIG. 2 for this condition withvoltage extending in the vertical direction and time extending in thehorizontal direction in the figure.

When the type of error illustrated in FIGS. 2 and 2a occurs, thephotoelectric sensing. device 36b, which senses along the line C of FIG.2, will first sense the presence of the circumferential register mark24a and, following the sensing of the register mark 24a, the sensingdevice 36a, which senses along the line C, will sense the presence ofthe circumferential reference register mark 28a. Since the unit registermark 24a was sensed prior to the sensing of the reference register mark28a, the control system 40 of FIG. 1 will determine that a leadingcircumferential error has occurred. The time that elapses between thesensing of the control register mark 24a and the sensing of thereference register mark 28a indicates the circumferential registrationerror which corresponds to the distance d1 of FIG. 2. The pulses fromthe sensor 36a in response to the reference marks 28a, 28b areillustrated in displays A and B of FIG. 2a and designated by thereference numerals 50 and 52, respectively. Similarly, the pulses fromthe sensor 36b are shown in displays C and D of FIG. 2a and designatedby the reference numerals 54 and 56, respectively. The time period whichelapses between the leading edges of the circumferential pulse 54 fromthe sensor 36b and the reference circumferential pulse 50 from thesensor 36a is illustrated by a pulse 58 shown in display E of FIG. 2a,the duration of which is proportional to the distance of FIG. 2.

This pulse is utilized to open a pulse gate to pulse a counter in thecontrol system 40 to establish the circumferential error therein priorto the sensing of the lateral reference register mark 24b.

Following the sensing of the circumferential register marks 24a, 28a,the sensors 36a, 36b will then operate to sense the lateral registermarks 28b, 24b, respectively. If as in the assumed case, there is aleading circumferential error, the control register mark 24a would leadthe reference mark 28a and this would give a false indication of lateralmisregister since the lateral registration mark 24b will pass the sensor36b before the lateral reference register mark 28b passes the sensor36a. Accordingly, even if there is no lateral registration error, thesensors will see an apparent error caused by the circumferential error.If in fact there is a lateral error, for example, a lateral error whichwould shift the marks 24a, 24b for the unit 12A to the solid lineposition shown in FIG. 2, the reference mark for lateral registration28b will produce pulse 52 (see display B in FIG. 2a) which occurs intime ahead of the pulse 56 (see display D in FIG. 2a) which occurs whenthe mark 24b printed by the unit 12A reaches the sensor 36b.Accordingly, the apparent lateral error will be decreased and will be asshown by pulse 60 in display F in FIG. 2a. To obtain the true lateralerror in this case, the circumferential error must be added to theapparent lateral error as represented by the pulses 64a and 64b indisplay G in FIG. 2a.

The control system 40 algebraically adds the circumferential error,which is represented by the pulse 58, to the apparent lateral error,which is represented by the pulse 60 to obtain the true lateral error,which is represented by the combined pulses 64a, 64b. In other words,the true lateral error is represented by the sum of the distances d1 andd2 of FIG. 2, and not merely by the distance d2, and this distance ismeasured by the control system 40.

In FIGS. 3 and 3a, a lagging circumferential misregistration error and alagging lateral misregistration error are illustrated. In this instance,the sensing device 36a will sense the reference register mark 28a andproduce pulse 50' (see display A in FIG. 3a) prior to the sensing of thecontrol register mark 24a by the sensing device 36b and the occurrenceof pulse 54 in display C in FIG. 3a. The time between pulses 50' and 54'is represented by the pulse 58' which extends between the leading edgeof the pulse 50' and the leading edge of the pulse 54 and the width ofthe pulse 58' represents the lagging circumferential error thatcorresponds to the distance d1 of FIG. 3.

The lateral reference register mark 28b is sensed along the subtractline C by the sensing device 36a to produce the pulse 52' and thelateral control register mark 24b is sensed along the line C by thesensing device 36b to produce the pulse 56' at a time subsequent topulse 52'. The duration of the pulse 60' of FIG. 3a which extendsbetween the leading edge of the pulse 52' and the leading edge of thepulse 56' represents the apparent lateral registration error. Since thetrue lateral error in FIG. 3 is the distance d2 minus the distance d1,the control system 40 must substract the circumferential registrationerror, as represented by the pulse* 58' from the apparent lateral error,as represented by the pulse 60', in order to obtain the true lateralregistration error which is represented by the pulse 62.

The control circuitry 40 includes a lateral error counter 102 and acircumferential error counter 108 for each of the upper and each of thelower printing units. The counters for the printing unit 12A are shownin FIG. 4b. It will be understood that there are no counters for thelast printing unit since it is the printing unit which prints thereference register marks 28a, 28b.

When the circumferential reference mark 28a arrives at its sensor 36abefore or after the circumferential mark 24a printed by the printingunit 12A, pulses will be applied to the circumferential counter 108 toindicate the magnitude of the circumferential error. These pulses willalso be applied to the lateral counter 102 to correct for the apparenterror which will occur in the lateral register as described above.Similarly, when the lateral register reference mark 28b arrives at thesensor 36a before or after the lateral register mark printed by aparticular unit, pulses will be applied to the lateral register counter102 for that unit to indicate the magnitude of the apparent lateralerror.

The counters 102,, 108 shown in FIG. 4b are for the printing unit 12Aand the description will proceed with reference to that unit. When thereference register mark 28a arrives at the sensor 36a before theregister mark 24a printed by the printing unit 12A, the referencecircumferential register mark 28a will activate gating to allow pulsesfrom a pulse generator 73 to be applied to the circumferential counterand to the lateral counter. The pulses from the pulse generator 73 willbe applied to the counters until the circumferential register mark 24aprinted by the printing .unit 12A arrives at the sensor 36b. At thistime the pulses to the counter 108 and to the lateral counter 102 willbe terminated in response to the sensing of the circumferential registermark. If the circumferential register mark printed by the printing unit12A arrives at the sensor 36b before the reference circumferentialregister mark arrives at the sensor 36a, the register mark 24a willinitiate the pulses to the counters and the reference mark 28a willterminate the pulses. Consequently, it can be seen that the number ofpulses supplied to the counting means 108 and the counting means 102will be indicative of the magnitude of the circumferential error.

Similarly, when the lateral register mark 28b arrives at the referencesensor 36a before or after the time that the lateral register markprinted by the printing unit 12A arrives at the sensor 36b, the pulsesfrom the sensor are utilized to initiate and stop pulses to the lateralerror counter 102. The pulses will be applied to the error counter 102to effect counting in one direction if the reference pulse arrives firstand to effect counting in the opposite direction if the lateral registermark 24b printed by the printing unit 12A arrives first.

In accordance with the preferred embodiment of the present invention,the registration of the units are not checked every cycle but areperiodically checked every Nth cycle, for example every eight cycles. Inthe illustrated embodiment, the press has a second pulse generator 78which generates one pulse for every press revolution with this pulseappearing on output 78a. The pulse generator 78 also generates a muchhigher number of pulses each revolution, for example 240 pulses, andthese pulses appear on an output terminal 78b.

The revolution output 78a is connected to a dividing circuit 79 whichprovides a signal on an output connection 79a every Nth revolution. Itis during the revolution when this output signal is present that thecontrol circuitry 40 may respond to signals from the sensor for theregister marks. When there is an output signal on the output 79a fromthe counter 79, the output pulses 78b are applied through a gate 82 to acounter 84 for selecting the period during the revolution when thecircuitry is capable of responding to the sensors. The counter 84 is amulti-stage binary counter and the third stage of the counter has beendesignated by the reference numeral 90 and the fourth stage by thereference numeral 92. The. counterstages each have Q and 6 outputs whichrespectively have a logic 1 signal thereon when the stage is set andreset, respectively.

After the counter 79 has received N pulses a signal appears during theNth revolution on its output 79a and this activates a one-shotmultivibrator to provide a signal to a flip-flop circuit 93 provided bytwo crossconnected NAND gates 94, 96. The reset input of the flip flopis provided by one of the inputs of the NAND gate 94and this inputnormally has a logic 1 input supplied by the Gsignal from the binarystage 92. As will be. appreciated by those skilled in the art, thebinary stage 92 normally has a logic 1 output on its Q output unless ithas been set in response to pulses applied to the counter. It requiressix pulses to set the binary stage 92 when the counter starts countingfrom 0 where all stages are in their reset states. The output from theoneshot multivibrator 85 is applied to the 1 input of the NAND gate 96through an inverter 97 so that there is normally a logic 1 input fromthe divide by N circuit 79 to the NAND gate 96. This input coupled withthe logic 1 input to the NAND gate 94 from the binary stage 92 normallymaintains a 0 logic level on the output 960 from the NAND gate 96 whichis the output of flip flop 93. When the signal appears on the output ofthe divide by N circuit 79 and triggers the one-shot multivibrator 85,the input to the NAND gate 96 becomes a logic and the output from theNAND gate becomes a logic 1.

A logic 1 on the output of the NAND gate 96 of window flip flop 93conditions inputs 98a, 104a of circumferential and lateral cycle gates98 and 104, respectively, to be activated in response to logic 1 inputson their second terminals 98b, 104b, respectively. The gates 98, 104direct the application pulses to the counters 102, 108 during theportions of the cycle for sensing circumferential and lateral errors,respectively, and when the gate 98 is activated pulses are applied inresponse to the sensing of an error to both the circumferential counter108 and the lateral counter 102. When the gate 104 is activated, pulsesare only applied to the lateral counter. The gate 98 for conditioningboth counters 102, 108 to receive pulses has its second input 98bconditioned by the Q by the third stage 90 of the binary counter 84.Consequently, the gate 98 is conditioned while the counter has a countof 0 to 3 since the third stage of the counter is set in response to thefourth pulse applied to the counter input when the counter startscounting from 0. When the third stage 90 is set in response to thefourth pulse, the logic lis lost on the input 98b and established on theinput 104b of the gate 104 which is connected to the Q output of thebinary stage 90. The conditioning of the gate 104 with the logic 1conditions the gating for the lateral counter so that it may receivepulses if an error is sensed by the sensors 36a, 36b.

The logic 1 output of the window flip flop 93 formed by the gates 94, 96is also applied to the reset terminals of a pair of direction flip flops114, 115 formed by NAND gates 116, 120 and 121, 122, respectively, fordetermining the sense of the error, i.e., whether the error is leadingor lagging. As long as the inputs to the NAND gates 116, 121 from thewindow flip flop 93 is at a 0, the flip flops 120, 121 will set andreset with a change in signal on inputs 120a, 122a to the gates 120,

122, respectively. However, the inputs to the gates 120, 122 on theinputs 120a, 122a are clamped at a high level except during the windowperiod by the output of gates 123, 125 between the circuits 74, 76. Thegates 123, 125 are NAND gates so that the gates have a high output aslong as one of the inputs is low. One of the inputs of each gate 123,125 is connected to one of the pulse shaping circuits 74, 76 for thesensors 36a, 36b, respectively, while the other input is connected tothe output 96a of the window flip flop 93 so that a high level output ismaintained to the NAND gates 120, 122 as long as a logic 0 appears onthe output 96a. Consequently, the output from the flip flop 93 rendersthe flip flops 114, 115 nonresponsive to signals from the sensors 36a,36b except during the window period and the flip flops are held in acondition where there is a logic 0 on the outputs 1220, 1200 of the flipflops 115, 114, respectively, and a logic 1 on the outputs 1160 and 1210of the flip flops 1 l4, 1 15, respectively.

When the logic 1 appears on the output 96a from the flip flop 93 toinputs 116a, 121a of the NAND gates l 16, 121, there will be no changein the NAND gates of either of the flip flops 114, 115 until the logic 1from a sensor changes to a logic 0. This is true because the gates 1 16,121, each have a logic 0 on an input from the associated NAND gate whichholds the output of gates 121, 116 at a logic 1 regardless of the logiclevels on inputs 116a, 121a from the window flip flop. However, whenthere is a logic 1 on the inputs 116a, 121a and the signal from one ofthe sensors 36a, 3612 changes to a logic 0, the corresponding flip flop114 or 115 will switch states. If the input to NAND gate 122 from sensor36a changes to a logic 0, the output 1220 of NAND gate 122, and of theflip flop 115, changes to a logic 0 which in turn will apply a logic 1to one input of the NAND gate 121 to change the flip flop output 1210from a logic 1 to a logic 0. Since the NAND gate 121 now has two logic 1inputs, the second input to the NAND gate 122 is a logic 0.Consequently, any change in the change in level on the input 122a to thesignal on input 122a to the flip flop 115 will not change the state ofthe gate 122 or the flip and the flip flop remains set for the entirewindow period, i.e., as long as a logic 1 is maintained to the gate 121from the flip flop 93. Consequently, if the sensor 36a first senses themark printed by the printing unit 18A, the flip flop 115 will change itsstate so that alogic 1 appears on its output 1220 and a logic 0 appearson its output 1210. The control flip flop 114 will remain in the samestate that it was at the beginning of the window period and will have alogic 0 on its output 1200 and a logic 1 on its output 1160. In thiscondition the logic ls on the output 1160 and the output 1220 from theflip flops 114, 115, respectively, are utilized to activate a NAND gate126 of a pair of direction sensing NAND gates 124, 126 to change theoutput of the NAND gate 126 from a l to 0. Normally, the NAND gates 124,126 have a 1 output since the NAND gates 124 have-respective inputsconnected to the outputs 1200, 1220 of the flip flops 1 14, 115 whichnormally have logic 0 thereon and respective inputs connected to theoutputs 1210, 1160, respectively, which normally have logic ls thereon.Consequently, when one of the flip flops 114, 1 15 changes states, forexample flip flop 115, the input therefrom to gate 126 changes to alogic 1 to change the output 1260 from the gate to a logic 0. The inputto gate 124 from flip flop 115 also changes from a logic 1 to a logic 0but this does not activate the gate since its input from the gate offlip flop 114 is a logic 0.

The direction NAND gates 124, 126 have their outputs 1240, 1260connected to inputs of a direction sensing flip flop 129 made up of NANDgates 128, 130. The output 1300 of the NAND gate 130 is used to signalwhether the error is leading or lagging, that is whether the referencecontrol mark or the reference register mark was first sensed by itsrespective sensor. In the illustrated embodiment if there is a logic 0on the output 1300 it signifies that the mark printed by the printingunit preceded the mark printed by the reference sensor and that theerror is therefore leading while if a logic 1 appears it indicates thecontrary.

The outputs of the direction sensing gates 124, 126 are also used togate pulses to the counters when an error is sensed. The outputs 1240,1260 of the direction sensing gates 124, 126 are applied to the inputsof the NAND gate 138. Normally, the NAND gates 124, 126 supply logic 1signals to the NAND gate 138 and this normally provides a logic 0 on theoutput 1380 from the NAND gate 138. The logic 0 on the output of NANDgate 1380 is applied to one input 142a of a NAND gate 142 which has itssecond input 142b connected to the output of the pulse generator 73.Since the input from the NAND gate 138 to the pulse gate 142 is normallya logic because both NAND gates 124, 126 have a logic 1 on theiroutputs, when one of the flip flops 114, 115 is activated by a signalfrom its sensor, the change in input from the gate 124, or the gate 126depending on which of the flip flops is first activated from a logic 1to a logic 0 causes the output 1380 from the gate 138 to change to alogic 1 to supply a logic 1 to one input of the pulse gate 142.Consequently, as the input of the pulse gate 142 which is connected tothe pulse generator 73 changes level, the output of the gate 142 willalso change level and the pulses will be transmitted by the gate untilthe output of the gate 138 is again a logic 0. The output of the gate1380 will return to a logic 0 when the second register mark passes itssensor.

In the assumed case where the register mark from the printing unit 12Apasses its sensor 36b after the reference register mark passes itssensor 36a, the arrival of the register mark from unit 12A at the sensor36b will cause the activation of the flip flop 114 to change the logic 0on its output 1200 and the logic 1 on its output 1160 to logic 1 andlogic 0, respectively. This changes the input from the flip flop 114 tothe NAND gate 126 from a l to a O to return its output 1260 to its 1condition. Also, the inputs to the NAND gate 124 now have a logic 1 anda logic 0 on its inputs since the flip flop 1 15 which was initiallyswitched in response to the pulse from the sensor 36b to a state wherethere was a logic 0 on the output 1210 to provide two logic 0 s to NANDgate 124. When the flip flop 114 is triggered to change its output fromgate 1200 to gate 124 from a O to a l, the NAND gate 124 now has a logic1 input and a logic 0 which still provides a logic 1 output which is thesame as the output for a normal condition. This logic 1 with the logic 1output of the NAND gate 126 because of the logic 0 from the flip flop114 and the logic 1 input from the flip flop 115 provides two logic 1inputs to the gate 138 and causes a logic 0 to appear on the output ofthe NAND gate 138 closing the pulse gate 142. Consequently, it can beseen from the above description that for the described situation, pulseswill be passed by the pulse gate 142 only during the time period betweenthe pulses from the sensors 36b, 36a.

It will also be readily appreciated that if the mark from the printingunit 12A arrives at its sensor 36b before the reference mark arrives atsensor 36a to indicate a leading error, the flip flop 114 will be firstactivated to change the input to the NAND gate 124 so that both of itsinputs are a logic 1 and its input to gate 126 so that both of itsinputs are logic 0. When this happens, the output of the NAND gate 138will change from a O to a l and open the pulse gate, Also, theconnection from the NAND gate 124 to one input of the NAND gate 128 ofthe direction sensing flip flop 129 will change from a l to a 0. Achanging of the input 128 from a normally 1 to a 0 will cause aswitching of the flip flop if the flip is in a state where there is alogic 0 on the output from gate 128 and logic 1 from gate 130. With theNAND gate 128 of the flip flop in a state with a 1 input from the NANDgate 130 and from the gate 124, when the NAND gate 124 changes itsoutput from a l to a O, the output of NAND gate 128 of flip flop 129changes to a l and this changes the output 1300 from the gate 130 from al to a 0. Consequently, if the direction sensing gate 124a is changed tohave a logic 0 on its output to indicate a leading error, the directionsensing flip flop changes from its state to have a 1 on its output 1280and a 0 on its output 1300. If once set in this state, it will so remainuntil the gate 1260 is activated to establish a logic 1 to gate 130 anda logic 1 on output 1300 of the gate.

ln the assumed case, when the mark 24a of unit 12A passes the sensor36b, the output from the sensor changes the flip flop 114 to provide alogic 1 on its output 1200 and a logic 0 on its output 1160. When theoutput from the NAND gate 1160 of flip flop 114 changes from a l to a 0,it switches the output of the NAND gate 126 to a 1. Since the NAND gate124 also has a logic 1 output at this time, the pulse gate 138 will beswitched to a logic 0 to close the pulse gate 142.

From the foregoing description it can be seen that the NAND gate 124 hasone input connected to the flip flop 1 14 which normally receives alogic 0 from the flip flop. A second input of the NAND gate 124 isconnected to the flip flop 115 and normally has a logic 1. Similarly,the NAND gate 126 has an input connected to the flip flop 114 to have anormal logic 1 input and an input connected to the flip flop 115 tonormally have a logic 0. Consequently, if one of the flip flops changesstate, one of the NAND gates 124 will have a logic 1 applied to bothinputs and the other NAND gate will have logic 0 applied to both inputs.If the flip flop 114 changes state, the NAND gate 124 will have bothinputs at a logic 1 level while if the flip flop 115 first changes statethe NAND gate 126 will have both inputs at a logic 1 level. The outputof a NAND gate is not changed when a logic 0' is maintained on one ofthe in puts even though the other input changes from a logic 1 to alogic 0. Consequently, if the flip flop 114 is first activated inresponse to a register mark, the NAND gate 124 will be activated tochange its output from a logic 1 to a logic 0 while the NAND gate 126will not be activated in response to the change of its input from theflip flop 1 14 from a l to a 0. Conversely, if the flip flop 115 isactivated before the flip flop 114, the NAND gate 126 will have logic lson both. of its inputs and will be activated to change its output from alogic 1 to a logic 0 while the NAND gate 124 will not be activated.-

l-lowever, when the other flip flop is activated in either case, theNAND gate 124 or 126 which had been activated will lose the logic 1 fromthe flip flop which is activated second to return its output to alogic 1. The other NAND gate will not be activated because when only oneof the flip flops 114, 115 is switched in response to a signal, thenonactivated one of the gates 124, 126 has two logic 0 inputs and thechanging of one of the logic 0 to a 1 does not alter the output of thegate.

It will be noted that once one of the flip flops 114, 115 is switched tochange its state, the inputs from the sensor to the flip flop losescontrol since the gate receiving a signal from the flip flop 95 has twologic 1 signals applied to its inputs to maintain its output at a logic0. In the case of the flip flop 114, this maintains one input to theNAND gate at a logic 0 regardless of the level on the input from thesensor 36a. Similarly, when the flip flop is switched, the NAND gate 121has two logic 1 signals on its inputs and its output is a logic so thatthe level on the input 122a to the gate 122 has no effect on the outputof the gate.

After the flip flops 114, 115 have been set it is necessary to reset theflip flops before a next sensing operation. This is done by changing thelevel from the direction flip flop 93 to the inputs 1 16a, 121a of theflip flops 114, 115 to a logic 0. When these inputs are changed to alogic 0 with logic 1 signals on their inputs 120a, 122a, the flip flopsreset with the gates 122, 120 having two logic 1 signals applied theretoto provide logic 0 signals from the NAND gates 120, 122 to the directionsensing gates 124, 126.

Since the circumferential register marks are to be sensed first and thenthe lateral register marks, it is necessary to reset the flip flops andthe circuitry after the sensing of the circumferential register mark andthe measurement of any error by opening the pulse gate 142 for a timecorresponding to the error. The circuitry is reset by a one-shotmultivibrator 149 which is connected to the Q output of the third stage90 of the binary counter 84. Consequently, when this output changes froma logic 1 to a logic 0, the one shot is activated to change its outputfrom a logic 1 to a logic 0. The 6 output of the one shot is connectedto the output 96c of the window flip flop 93 and when it changes to alogic 0 it changes the signal from the flip flop 93 to a logic 0 toreset the flip flops 114, 115. After the resetting, the circuit is thenin condition to sense the lateral register marks and will do so untilthe fourth stage flip flop 92 is activated to lose the logic 1 signal Ion its 6 output. At this time, the window flip flop 93 is reset and thewindow signal is lost to the flip flops 114, 115 and the gates 123, 125are clamped in a condition where they will not respond to the sensors36a, 36b.

As explained hereinbefore, it is necessary to correct the apparentlateral error for any circumferential error. Consequently, pulses whichindicate the circumferential error are applied to the lateral updowncounter as well as to the circumferential up-down counter. To this end,the pulse gate 142 is connected directly to the clock terminal 102a(FIG. 4b) of the lateral up-down counter 102 through an OR gate 150 sothat any pulses which are passed by the pulse gate will be applied tothe lateral up-down counter. These pulses are also applied to the clockterminal 108a of the circumferential up-down counter 108 through a NANDgate 151 and an OR gate 152. The NAND gate 151 normally has a logic 0 onan input l51b whose logic level is controlled by the output of thecircumferential cycle gate 98 (FIG. 4a). The output of the gate 98 isapplied to the input 151b through an inverter gate 153 and this gatewill have a logic 1 thereon for the period during which the binarycounter 84 counts from 0 to 4. On the fourth count, the third binarystage 90 is triggered from its Q condition to its Q condition so thatthe output from the circumferential gate 98 becomes a logic 1 to changethe output of the inverter gate 153 to a logic 0 which renders thecircumferential gate 151 for counter 108 nonresponsive to pulses fromthe pulse generator 142. Consequently, the circumferential register 108can only be stepped from the pulse gate 142 during the period that thecounter is counting from O to 4 and on the occurrence of the fourthpulse, the circumferential gate is closed. The timing is set so that theregister marks will normally be passing the sensors during this sensingperiod.

The direction of counting in the counters 102, 108 in response to anerror pulse is determined by a condition of the flip flop 129. If thereference sensor arrives at the sensor 36a in advance of the registermark printed by the unit 16A, the flip flop 129 will have a logic 1 onits output 130a to indicate that the printing unit is lagging thereference mark. This logic 1 is applied to the input of a NAND gate(FIG. 4b) to change its output from a logic 1 to a logic 0 since theother input of the NAND gate 155 is connected to the window flip flop93. The output of the NAND gate 155 is connected to the count-upterminal 108b of the circumferential counter 108 and to the countdownterminal 1080 of the up-down counter through an inverter gate 156.Consequently, when the gate 155 has a logic 1 on its output the countercounts in an up direction and when it has a logic 0 on its output thecounter counts in the down direction.

A second NAND gate 157 has its output wired to the output of the NANDgate 155 so that these NAND gates constitute a wired OR arrangement. Ina wired OR arrangement, one of the gates is maintained with a logic 1 onits output and the other gate then assumes control and the output fromthe two gates is either a logic 1 or a logic 0 depending on the outputof the other gate. The gate 157 at this time will have a logic 0 on oneinput since the output 960 of the window flip flop 93 is connected toone input of the NAND gate 157 through an inverter NAND gate 158 (FIG.4a) so that a logic 0 is applied to the NAND gate 157 during the windowperiod. This assures a logic 1 on the output of the gate. The NAND gatehas its other input connected to a greater than 0 terminal 108d toreceive a l on the other input when the count in the counter is greaterthan 0. The purposes of gate 157 will be explained hereinafter.

As explained above, the output 130c of the flip flop 129 is used tocontrol the direction of counting of the circumferential up-down counter108. The output 128c of the flip flop 129 is similarly utilized tocontrol the direction of counting of the lateral up-down counter and isconnected to one input of a NAND gate 160 which has its output connectedin a wired OR relation ship with NAND gates 161, 162. The outputs ofthese NAND gates are connected directly to the count-up terminal 102b ofthe up-down counter 102 and to the countdown terminal 102v through aninverter 163. Consequently, the logic 1 or a 0 condition at the outputof these gates causes the counter to count in different directions.During the circumferential register mark sensing period, the NAND gates161, 162 will have logic 1 outputs so that the NAND gate 160 controlsthe signal level to the count-up and countdown terminals 102b, 1020. TheNAND gate 160 has an input 160a controlled by the output of thecircumferential gate 98 so that when there is a logic 1 on the output ofinverter 153 to signify the circumferential register mark sensingperiod, the input to NAND gate 160 is a 1 level so that the input toinput 160b of NAND gate 160, which is from the direction sensing flipflop 129, controls the output of the NAND gate 160. The output of theNAND gate 160 will have a logic 1 if the direction sensing flip flopindicates a lagging circumferential error and a logic 0 if a leadingerror is indicated since the gate 128c of flip flop 129 has a 0 outputfor a lagging error and a 1 output for a leading error.

As will be understood from the foregoing, the pulses which are added tothe circumferential counter when error occurs are also added to thelateral updown counter to count the counter in the proper direction tocorrect the apparent error which will occur in the counter because ofthe circumferential error. For example, since the lateral up-downcounter 102 is normally counted in an up direction when there is alateral error caused by the mark printed by the printing unit 16Alagging the reference mark printed by the last unit 18A, the signal fromthe NAND gate 160 conditioned by the circumferential gate will cause thepulses added during the circumferential gate sensing period to count thecounter in a down direction in a situation where the circumferentialmark printed by the printing unit 16A is lagging the reference mark andthe input to the direction count gate 160 from the direction flip flop129 is a logic 0. Then when the apparent error of lateral registercaused by circumferential misregistration is sensed during the lateralsensing period, the direction count gate 161, as is further explainedhereinafter, will cause the counter to count in an up direction tosubtract the same error from the counter and to arrive at a zero errorin the absence of any actual lateral misregistration.

When the third binary stage 90 is triggered to its Q condition on thefourth pulse applied to the counter after the start of the counterperiod, the logic 1 on the Q output of the stage is applied to the cycleNAND gate 104 to render the lateral error circuitry effective during alateral error sensing period. The output of the NAND gate 104 isconnected through an inverter 165 to one input 161a of the NAND gate161, the NAND gate having its input 161b connected to the output 130a ofthe direction sensing flip flop 129. At this time, the NAND gates 160,162 will have a logic 1 output because of the logic on the output of theinverter 153 from the circumferential gate 98 and the logic 0 on theoutput of NAND gate 158 whose input is connected to the window flip flop93. Accordingly, the logic level on the output of the NAND gate 161controlsv the direction of counting on the up-down counter during thelateral error sensing period and this level is controlled by the signallevel on the output 1300 of the direction sensing flip flop 129.Consequently, during the error sensing period, any pulses which arepassed by the pulse gate 142 and applied to the clock terminal 102a ofthe up-down counter 102 will count the counter in a direction determinedby the direction sensing flip flop 129. If the error is a lagging error,the output of gate 161 is a logic 0 and the counter counts down while ifa leading error, the counter counts up. These pulses are not applied tothe circumferential updown counter because the NAND gate 151 now has alogic 0 on the input controlled by output of the circumferential cyclegate 98.

The lateral error sensing period will continue from count 4 of thecounter 84 until the binary stage 90 of the counter is reset which willoccur on the eighth count after the star of the counting period. Theresetting of the binary stage 90 eflects a setting of the binary stage92 to cause the logic level on the Q binary output stage 92 to changefrom a logic 1 level to a logic window flip flop 93 changes to a logic 0to reset the flip flop and change the output of the NAND gate 94 to alogic 0 which in turn changes the output 96c from the NAND gate 96 to alogic 0 to provide a logic 0 output to the control circuitry from thewindow flip flop 93. This logic 0 prevents the circuitry from respondingto the sensors as hereinbefore described and since the pulse gate 142has been closed, no pulses can be applied to the up-down counters untilthe next window period is initiated by the divide by N circuit 79.

Following the completion of the 16th count the logic 1 signal to theNAND gate 94 of flip flop 93 from the 6 terminal of the binary stage 92of the counter 84 will be re-established but this will not effect thewindow flip flop 93 since at that time the NAND gate 96 of the flip flopwill have a logic 0 on its input to the gate 94 so that the signallevegm the input of the NAND gate 94 connected to the Q terminal of thebinary stage 92 of the counter 84 has no eflect on the flip flop so longas the level of signal to gate 96 from the one-shot multivibratorremains at a logic one.

After the window period, the up-down counters for the unit 16A are tocontrol the corresponding stepping motors 37, 39 to correct for anymisregister. When a count is registered in one or both of the countersafter the window period, pulses are supplied to the correspondingstepping motor and for each pulse applied to the stepping motor, acorresponding pulse is applied to the counter to count the countertoward its zero or middle count. When the counter is at 0, gates areclosed to stop the application of pulses to the stepping motor andcorrection has been effected.

To this end, the lateral up-down counter has an equal zero terminal 102eand the circumferential updown counter 108 has an equal zero terminal108e. The equal zero terminal l02e is connected through an inverter 174to one input of a NAND gate 176 whose output is connected to the OR gatefor the clock terminal 102a of the lateral up-down counter. When thecount in the lateral up-down counter is equal to 0, a logic 1 appears onthe terminal l02e and when it is different from 0, a logic 0 appears onthe terminal. When a logic 0 is on the terminal 102e, theNAND gate 176is conditioned to pass pulses applied to its input 176k. The pulses areapplied to the input 17Gb from the pulse generating terminal 78b of thepulse generator 78 through a NAND gate 178. One input of the NAND gate178 is connected to the terminal 78b while the second input of the NANDgate 178 is controlled by the window flip flop 93 which has its output96c connected to input of the gate 178 through an inverter 168.Consequently, the input of the NAND gate 178 controlled by the windowflip flop has a logic 1 thereon when the window is closed and a logic 0thereon when the window is opened. This prevents pulses from beingapplied to the stepping motor 37 during the window period. When thewindow period is over and there is a count in the counter, pulses willbe applied to the NAND gate 176 and in turn to the OR gate 150 and theclock terminal of the lateral up-down counter 102 if there is a count inthe counter so that the logic level on the equal to zero terminal 102eis a logic 0.

The pulses from the NAND gate .176 are also applied to stepping motorgates 180, 181 for operating the stepping motor in a clockwise and acounterclockwise direction, respectively. If the count in the up-downcounter is greater than 0, a logic level 1 appears on its greater thanterminal 102d, and this terminal is connected to one input of the NANDgate 180 so that pulses from the NAND gate 176 will be applied to thestepping motor circuitry to step the motor in a clockwise direction ifthe count in the counter is greater than 0. The greater than 0 terminal102d is also connected to one input of the NAND gate 181 through aninverter 183 so that if the count is not greater than 0 and a logic 0appears on the terminal 102d, a logic 1 is applied to one input of theNAND gate 181 from the gate 183 and pulses from the pulse gate 176 willbe passed from the pulse gate to the motor control circuitry to step themotor in a counterclockwise direction. Consequently, it can be seen thatif, after the window period, there is a count in the lateral counter,the pulse gate 176 is opened by the signal on the equal zero terminal,and the pulses are applied through either the clockwise gate 180 or thecounterclockwise gate 181, depending on the logic signal on the greaterthan zero terminal, to step the motor to correct the error andsimultaneously the pulses from the gate are applied to the clockterminal 102a of the lateral up-down counter to step the counter tozero. When the counter is stepped to zero, the logic level i on theequal zero terminal 102 e shuts the pulse gate 176 to pulses and thecorrection stops.

Similarly the equal zero terminal 108e on the circumferential up-downcounter is connected through a NAND inverter gate 184 to one input of aNAND gate 185 for supplying pulses to the circumferential updown counterand to the stepping motor 39 for effecting the circumferentialcorrection when there is a count in the counter. The pulse gate 185 hasits second input connected to the output of the gate 178 and its outputconnected through the OR gate 152 to the clock terminal 108a of theup-down counter and to clockwise gate 190 and counterclockwise gate 191for transmitting pulses to the control circuitry for the stepping motor39 to operate the stepping motor in a clockwise direction andcounterclockwise direction, respectively. The greater than zero terminal108d is connected to one input of the clockwise gate 190 to conditionthat gate to pass pulses when the count is greater than 0 and through aninverter 192 to an input of the NAND gate 180 for operating the motor ina counterclockwise direction to condition that gate to pass pulses whenthe count is less than 0. It can be seen that the circumferentialup-down counter supplies pulses to the stepping motor to effect thecorrection in the same manner as was the case with the lateral up-downcounter after the window period is over and an error has beenregistered. As in the case of the lateral updown counter, when thecircumferential counter is counted to 0, the logic 1 level on the equalzero terminal closes the pulse gate 185 to terminate the correction.

It will be noted that the greater than 0 terminal controls the directionof counting of the counter for the pulses from the gate 174 in the caseof the up-down counter 102 and from the gate 185 in the case of theup-down counter 108. In the case of the lateral updown counter, thegreater than 0 terminal 102d is connected to one input of the NAND gate162 which has a logic 1 on its other input at the end of the windowperiod. Since the NAND gates 160, 161 for controlling the direction ofcounting of the terminal have, at this time, a logic 1 on their outputs,the NAND gate 162 controls the direction of counting and its output hasa logic 0 or a logic 1 thereon depending upon the signal on the greaterthan zero terminal. If a logic 1 appears on the terminal, the output ofthe NAND gate 162 is a logic 0 to cause the counter to count down. Ifthe count in the counter is less than zero, the counter will count upsince the greater than 0 terminal will have a logic 0 thereon to providea logic 1 on the output of NAND gate 162 to effect a counting up of thecounter.

It will be noted that the window period is initiated every N revolutionsof the press by the one-shot multivibrator 85. This pulse is a pulse ofshort duration and is applied to reset all the counters except thedivide by N counter as well as to set the window flip 93 to conditionthe control circuitry to respond to the sensor marks during the windowperiod. The resetting of all of the counters at the start of the periodassures a zero setting in all counters and, in the case of counter 84,-proper cycling of the sensing periods. It will be further noted that thewindow flip flop is reset on the eighth count of the counter 84 and whenreset to. terminate the window period, the logic 1 input to the gate 96of the flip flop 93 prevents changes in logic levels on the Q terminalof stage 92 of the counter from changing the flip flop 93 and thecounter may be allowed to count continuously since it is reset at thebeginning of each window period.

Changes in the cycle flip gating 98, 104 will have no effect if thecounter operates outside of the window period.

From the foregoing,'it can be seen that the lateral register mark hasbeen compensated for the error introduced by circumferentialmisregister. It will be appreciated that the illustrated embodiment hasadded or subtracted pulses from the lateral counter from the time thepulses are applied to the circumferential counter, the circumferentialpulses could be counted, the lateral pulses and an algebraic operationperformed to obtain the true lateral error before the correction ismade. Also, the circumferential error could be inserted into the counterby parallel techniques after it has been established in thecircumferential counter or the circumferential correction could first bemade and the feedback pulses for the circumferential correction ap pliedto the lateral error counter to correct the lateral error of the counterat that time and a lateral correction made only if there is a count inthe counter after the circumferential misregistration has beencorrected.

From the foregoing, it will also be appreciated that if the marks are inregistry, the flip flops 114, will be switched simultaneously and whenthis happens the condition of the circuit will be the same as that forthe circuit after both flip flops have been triggered in sequence whenthere is a misregister. It will be recalled that when both flip flopshave been switched, the NAND gates 124, 126 each have a logic 1 on theiroutput which closes the pulse gate 142.

Although the present invention has been described with reference to anembodiment thereof, it is to be understood that other embodiments andvariations of the 17 present invention will apparent to those skilled inthe art and it is intended that these be included within the scope ofthe appended claims.

Moreover, in accordance with the preferred embodiment, the frequency ofthe pulses is dependent on the speed of the press so that the pulses tothe counters for a given error will be constant. In the illustratedembodiment, an analogue signal representative of pulse speed isconverted to a pulse train having a frequency dependent on the magnitudeof the signal.

What is claimed is:

1. In a machine for operating on stock moving through the machineincluding first adjusting means for making a first adjustment of saidstock relative to the operation performed by said machine on said stockwith respect to afirst degree of freedom, second adjustment 'means formaking a second adjustment of said stock relative to the-operation ofsaid machine on said stock with respect tov a second degree of freedom,sensor means for sensing a first register mark on said stock whichindicates the relationship of said stock to the operation of saidmachine performed thereon with respect to said first degree of freedomand for sensing a second register mark on said stock to indicate therelationship of the stock to the operation of the machine with respecttosaid second degree of freedom, changes in the relationship of said stockto the operation of said machine with respect to the second degree offreedom effecting a change in the sensed relationship of said first markindependently of a change in therelationship of the machine and stockwith respect to said first degree of freedom, and means responsive tosaid sensor means for ascertaining errors in the adjustment of saidfirst and second adjusting means andproviding first and second errorsignals for use in correcting said firstand second adjusting means independency on the sensing of said first and second marks including meansresponsive to the sensing of said second mark for compensating saidfirst error signal for .error introduced by changes with respect to saidsecond degree of freedom.

2. In a machine as defined in claim 1 wherein said means responsive tosaid sensor means comprises means responsive to said first and secondmarks for providing first and second control signals having a timeduration in accordance with the magnitudes of error to be corrected bysaid first and second adjusting means, respectively, and integratingmeans responsive to the time duration of said first control signal toprovidean error indication for said first. adjusting means andresponsive to the time duration of said second signal to compensate thesaid error indication to derive said first error signal in dependency onsaid first and second marks.

3. In a machine as defined in claim 2 wherein said integrating meanscomprises a pulse counter and means for transmitting pulsesto saidcounter during saidfirst control signal to register an error therein independency on said first mark and means for transmitting pulses duringsaid second control signal to establish a count for compensating thecount which is established during said first signal.

4. In a machine as defined in claim 3 wherein said counter isincrementally pulsed during said first and second control signals toestablish a compensated error count therein.

first and second pulse signals indicating the time difference betweensaid reference pulse and said first and second marks and directionsignals for indicating the lead-lag relationship of the marks and thereference pulses, and a counter for counting pulses in a directiondepending upon said direction signals during the time duration of saidfirst and second pulse signals to provide said first error signal.

6. In a machine as defined in claim 5 wherein said reference meanscomprises means for providing first and second reference signals to becompared respectively with said first and second registration marks andsaid means responsive to said marks for providing said first and secondcontrol signals comprises circuit means actuated to two conditions byone of said reference signals and the corresponding one of said marks.

7. .In a machine according to claim 6 wherein said circuit means isactuated to first and second conditions to provide one of said first andsecond control signals in response to one of said registration signalsand the corresponding reference signal and includes means for resettingsaid circuit meansto a third condition for actuation to said first andsecond conditions in response to the other mark and correspondingreference signal to provide the other of said first and second signals.

8. In a machine according to claim 7 wherein said circuit meanscomprises first and second two-stage circuits, one of said circuitsbeing set :in response to the registration mark and the other of saidcircuits being set in response to the reference mark and said means forresetting said circuit comprising means for resetting said first andsecondtwo-stage circuits.

9. In a machine according to claim 8 wherein said circuit meansresponsive to said sensor meansincludes means responsive to theactuation of said first and second two-stage circuits to determine whichof the circuits is first actuated to determine the lead-lag relationshipof the reference mark and its corresponding registration mark.

10. In a machine according to claim 9 in whichsaid means responsive tosaid sensor means comprises means for inhibiting the response of saidcircuit means to said sensor means except for a predetermined period inthe operation of said machine in which a register mark is to be passingsaid sensor means.

11. A method of correcting a false error indicated by the sensing of aregistration mark for indicating the location of machine operation onthe work with respect to an adjustment in one direction when theposition of the mark on the work varies with the position of thereference to determine time intervals that the marks are late or earlyin passing the location to ascertain the error in the adjustment inaccordance with the time inof the image on the sheet materialtransversely of and in the direction of movement of the sheet materialthrough the press, the first mark being inclined relative to the line ofmovement of the sheet material through the press and the second markbeing transverse to the 'line of movement, sensing the marks at a fixedlocation to determine the time that the marks pass the location withrespect to a reference to determine registration errors transversely ofand in the direction of sheet movement and electrically combining theerror sensed in the adjustment transversely of and in the direction ofthe movement of the the sheet to provide a corrected transverse errorsignal when errors are introduced into the error signal because ofmisregistration in the direction of sheet movement.

13. A method as defined in claim 12 in which a signal is derived fromeach of said registration marks as it passes said sensing means and iscompared with reference signals for each mark indicating the time that lthe registration marks should be at the sensing means, the error in timebeing measured by pulsing a counter for registering the error in thedirection transversely of the sheet movement both during the timeinterval between the arrive of the first and second registration marksat the sensing means and their respective reference signals.

14. In a printing press for printing an image on sheet stock movingthrough the machine including first adjusting means for making a firstadjustment of said stock relative to the printing operation performed bysaid machine on said stock, second adjustment means for making a secondadjustment of said stock relative to the printing operation of saidmachine on said stock, sensor means for sensing a first register mark onsaid stock which indicates the relationship of the printed image on saidstock with respect to a first degree of freedom controlled by said firstadjustment and for sensing a second register mark on said machine toindicate the relationship of the printed image on said stock withrespect to a second degree of freedom controlled by said secondadjustment means, changes in the position of the image on said stockwith respect to the second degree of freedom effecting a change in thesensed relationship derived from said first mark independently of achange in the relationship of the image on the stock with respect tosaid first degree of freedom, means responsive to said sensor means forascertaining errors in the adjustment of said first and second adjustingmeans and providing first and second error signals for correcting saidfirst and second adjusting means including means responsive to thesensing of said second mark for compensating said first error signal forfalse errors introduced by errors in said second adjusting means.

15. In a method of operating a machine in which a cyclical workoperation is performed on stock moving in one direction through amachine with the work 0 rati n bein ontro led wit res ct to afirst deree offree om, ap pl ying first register r arks to said sFock whosetimes of arrival at a sensing station as compared to a referenceindicate the adjustment of the machine with respect to a first degree offreedom, the times of arrival of said first register marks at said firststation varying in accordance with the adjustment of the machine withrespect to a second degree of freedom, applying register marks saidstock whose time of arrival at said station with respect to a referenceindicates the adjustment of said machine with respect to said seconddegree of freedom, and sensing the times of arrival of said first andsecond marks at said station to provide error signals for controllingthe adjustment of the machine with respect to said first degree offreedom including compensating the error signal derived in dependency onthe arrival of said first register marks in accordance with the time ofarrival of said second register marks at said station to render theerror signal for adjusting the machine with respect to said first degreeof freedom independent of the adjustment of said machine with respect tosaid second degree of freedom.

16. In a method as defined in claim 15 wherein said first degree offreedom is transversely of the line of movement of the stock through themachine and the first register mark comprises a line which is inclinedwith respect to the line of movement.

17. In a method as defined in claim 16 wherein said second degree offreedom is along the line of movement of the said material through themachine.

1. In a machine for operating on stock moving through the machineincluding first adjusting means for making a first adjustment of saidstock relative to the operation performed by said machine on said stockwith respect to a first degree of freedom, second adjustment means formaking a second adjustment of said stock relative to the operation ofsaid machine on said stock with respect to a second degree of freedom,sensor means for sensing a first register mark on said stock whichindicates the relationship of said stock to the operation of saidmachine performed thereon with respect to said first degree of freedomand for sensing a second register mark on said stock to indicate therelationship of the stock to the operation of the machine with respectto said second degree of freedom, changes in the relationship of saidstock to the operation of said machine with respect to the second degreeof freedom effecting a change in the sensed relationship of said firstmark independently of a change in the relationship of the machine andstock with respect to said first degree of freedom, and means responsiveto said sensor means for ascertaining errors in the adjustment of saidfirst and second adjusting means and providing first and second errorsignals for use in correcting said first and second adjusting means independency on the sensing of said first and second marks including meansresponsive to the sensing of said second mark for compensating saidfirst error signal for error introduced by changes with respect to saidsecond degree of freedom.
 2. In a machine as defined in claim 1 whereinsaid means responsive to said sensor means comprises means responsive tosaid first and second marks for providing first and second controlsignals having a time duration in accordance with the magnitudes oferror to be corrected by said first and second adjusting means,respectively, and integrating means responsive to the time duration ofsaid first control signal to provide an error indication for said firstadjusting means and responsive to the time duration of said secondsignal to compensate the said error indication to derive said firsterror signal in dependency on said first and second marks.
 3. In amachine as defined in claim 2 wherein said integrating means comprises apulse counter and means for transmitting pulses to said counter duringsaid first control signal to register an error therein in dependency onsaid first mark and means for transmitting pulses during said secondcontrol signal to establish a count for compensating the count which isestablished during said first signal.
 4. In a machine as defined inclaim 3 wherein said counter is incrementally pulsed during said firstand second control signals to establish a compensated error counttherein.
 5. In a machine as defined in claim 2 wherein said meansresponsivE to said sensor means includes reference means providingreference signals for indicating the time said first and second marksare to be sensed when adjustment is proper, means for providing firstand second pulse signals indicating the time difference between saidreference pulse and said first and second marks and direction signalsfor indicating the lead-lag relationship of the marks and the referencepulses, and a counter for counting pulses in a direction depending uponsaid direction signals during the time duration of said first and secondpulse signals to provide said first error signal.
 6. In a machine asdefined in claim 5 wherein said reference means comprises means forproviding first and second reference signals to be compared respectivelywith said first and second registration marks and said means responsiveto said marks for providing said first and second control signalscomprises circuit means actuated to two conditions by one of saidreference signals and the corresponding one of said marks.
 7. In amachine according to claim 6 wherein said circuit means is actuated tofirst and second conditions to provide one of said first and secondcontrol signals in response to one of said registration signals and thecorresponding reference signal and includes means for resetting saidcircuit means to a third condition for actuation to said first andsecond conditions in response to the other mark and correspondingreference signal to provide the other of said first and second signals.8. In a machine according to claim 7 wherein said circuit meanscomprises first and second two-stage circuits, one of said circuitsbeing set in response to the registration mark and the other of saidcircuits being set in response to the reference mark and said means forresetting said circuit comprising means for resetting said first andsecond two-stage circuits.
 9. In a machine according to claim 8 whereinsaid circuit means responsive to said sensor means includes meansresponsive to the actuation of said first and second two-stage circuitsto determine which of the circuits is first actuated to determine thelead-lag relationship of the reference mark and its correspondingregistration mark.
 10. In a machine according to claim 9 in which saidmeans responsive to said sensor means comprises means for inhibiting theresponse of said circuit means to said sensor means except for apredetermined period in the operation of said machine in which aregister mark is to be passing said sensor means.
 11. A method ofcorrecting a false error indicated by the sensing of a registration markfor indicating the location of machine operation on the work withrespect to an adjustment in one direction when the position of the markon the work varies with the position of the stock relative to themachine in a degree of freedom controlled by a second adjustment, therelationship of the stock to the machine in the degree of freedomcontrolled by the second adjustment being indicated by the position of asecond registration mark, comprising the steps of sensing theregistration marks as they pass a fixed location, comparing theregistration marks with a reference to determine time intervals that themarks are late or early in passing the location to ascertain the errorin the adjustment in accordance with the time interval and modifying theerror derived in dependency on the first mark before making theadjustment as a function of the error derived in dependency on saidsecond mark.
 12. A method of registering images printed by a press ontosheet material comprising the steps of printing first and secondregister marks indicating the position of the image on the sheetmaterial transversely of and in the direction of movement of the sheetmaterial through the press, the first mark being inclined relative tothe line of movement of the sheet material through the press and thesecond mark being transverse to the line of movement, sensing the marksat a fixed location to determine thE time that the marks pass thelocation with respect to a reference to determine registration errorstransversely of and in the direction of sheet movement and electricallycombining the error sensed in the adjustment transversely of and in thedirection of the movement of the the sheet to provide a correctedtransverse error signal when errors are introduced into the error signalbecause of misregistration in the direction of sheet movement.
 13. Amethod as defined in claim 12 in which a signal is derived from each ofsaid registration marks as it passes said sensing means and is comparedwith reference signals for each mark indicating the time that theregistration marks should be at the sensing means, the error in timebeing measured by pulsing a counter for registering the error in thedirection transversely of the sheet movement both during the timeinterval between the arrive of the first and second registration marksat the sensing means and their respective reference signals.
 14. In aprinting press for printing an image on sheet stock moving through themachine including first adjusting means for making a first adjustment ofsaid stock relative to the printing operation performed by said machineon said stock, second adjustment means for making a second adjustment ofsaid stock relative to the printing operation of said machine on saidstock, sensor means for sensing a first register mark on said stockwhich indicates the relationship of the printed image on said stock withrespect to a first degree of freedom controlled by said first adjustmentand for sensing a second register mark on said machine to indicate therelationship of the printed image on said stock with respect to a seconddegree of freedom controlled by said second adjustment means, changes inthe position of the image on said stock with respect to the seconddegree of freedom effecting a change in the sensed relationship derivedfrom said first mark independently of a change in the relationship ofthe image on the stock with respect to said first degree of freedom,means responsive to said sensor means for ascertaining errors in theadjustment of said first and second adjusting means and providing firstand second error signals for correcting said first and second adjustingmeans including means responsive to the sensing of said second mark forcompensating said first error signal for false errors introduced byerrors in said second adjusting means.
 15. In a method of operating amachine in which a cyclical work operation is performed on stock movingin one direction through a machine with the work operation beingcontrolled with respect to a first degree of freedom, applying firstregister marks to said stock whose times of arrival at a sensing stationas compared to a reference indicate the adjustment of the machine withrespect to a first degree of freedom, the times of arrival of said firstregister marks at said first station varying in accordance with theadjustment of the machine with respect to a second degree of freedom,applying register marks said stock whose time of arrival at said stationwith respect to a reference indicates the adjustment of said machinewith respect to said second degree of freedom, and sensing the times ofarrival of said first and second marks at said station to provide errorsignals for controlling the adjustment of the machine with respect tosaid first degree of freedom including compensating the error signalderived in dependency on the arrival of said first register marks inaccordance with the time of arrival of said second register marks atsaid station to render the error signal for adjusting the machine withrespect to said first degree of freedom independent of the adjustment ofsaid machine with respect to said second degree of freedom.
 16. In amethod as defined in claim 15 wherein said first degree of freedom istransversely of the line of movement of the stock through the machineand the first register mark comprises a line which is inclined withrespect to the line of movement.
 17. In a method as defined in claim 16wherein said second degree of freedom is along the line of movement ofthe said material through the machine.